With continuous development of semiconductor integrated circuit technology, interconnect structures are often used for high-performance and high-density connections between semiconductor devices when critical dimensions of the semiconductor devices decrease to the sub-micrometer range. A parasitic resistance and a parasitic capacitance become easy to form in the interconnect structures. The subsequent parasitic effect can induce time delay in the transfer of metal wires. Significant increase in the resistance-capacitance (RC) delay due to a rapid increase in the length of the interconnects become a big challenge.
In the integration technology of the interconnects of the large-scale integrated circuits, two methods are used to overcome the parasitic effects of the interconnects. On one hand, a parasitic capacitance is proportional to a relative dielectric constant of insulating dielectrics in the interconnect layers. Conventional SiO2 dielectric materials are substituted by low-K dielectric materials, especially ultra-low K dielectric materials, to meet requirements of the rapid development of chips. On the other hand, copper has a relatively low resistivity, an excellent anti-electromigration property, and a high reliability. Copper can reduce the interconnecting resistance of the metal and then reduce the total delay in the interconnections. Correspondingly, copper interconnects with lower resistance have substituted the conventional aluminium interconnections.
However, semiconductor devices formed by current technologies have poor performance. The disclosed devices and methods are directed to at least partially alleviate one or more problems set forth above and to solve other problems in the art.